A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs

Citation

Stewart R, Michaelson G, Bhowmik D, Garcia P & Wallace A (2016) A Dataflow IR for Memory Efficient RIPL Compilation to FPGAs. In: Díaz-Martín J, Carretero J, Garcia-Blas J, Gergel V, Voevodin V, Meyerov I, Rico-Gallego J, Alonso P, Durillo J, Garcia Sánchez J, Lastovetsky A, Marozzo F, Liu Q, Bhuiyan Z & Fürlinger K (eds.) Algorithms and Architectures for Parallel Processing. ICA3PP 2016. Lecture Notes in Computer Science, 10049. ICA3PP 2016: Algorithms and Architectures for Parallel Processing, Granada, Spain, 14.12.2016-16.12.2016. Cham, Switzerland: Springer International Publishing, pp. 174-188. https://doi.org/10.1007/978-3-319-49956-7_14

Abstract
Field programmable gate arrays (FPGAs) are fundamentally different to fixed processors architectures because their memory hierarchies can be tailored to the needs of an algorithm. FPGA compilers for high level languages are not hindered by fixed memory hierarchies. The constraint when compiling to FPGAs is the availability of resources. In this paper we describe how the dataflow intermediary of our declarative FPGA image processing DSL called RIPL (Rathlin Image Processing Language) enables us to constrain memory. We use five benchmarks to demonstrate that memory use with RIPL is comparable to the Vivado HLS OpenCV library without the need for language pragmas to guide hardware synthesis. The benchmarks also show that RIPL is more expressive than the Darkroom FPGA image processing language.

Keywords
Domain specific languages; FPGAs; Data locality

• Published version