Conference Proceeding

Specification and Verification of Synchronous Hardware using LOTOS

Details

Citation

He J & Turner KJ (1999) Specification and Verification of Synchronous Hardware using LOTOS. In: Wu J, Chanson ST & Gao Q (eds.) Formal Methods for Protocol Engineering and Distributed Systems. IFIP International Federation for Information Processing, Vol. 28. FORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification, Beijing, China, 05.10.1999-08.10.1999. Amsterdam: Springer Verlag, pp. 295-312. http://www.springer.com/computer/artificial/book/978-0-7923-8646-9?detailsPage=toc

Abstract
This paper investigates specification and verification of synchronous circuits using DILL (Digital Logic in LOTOS). After an overview of the DILL approach, the paper focuses on the characteristics of synchronous circuits. A more constrained model is presented for specifying digital components and verifying them. Two standard benchmark circuits are specified using this new model, and analysed by the CADP toolset (Cæsar/Aldébaran Development Package).

StatusPublished
Title of seriesIFIP International Federation for Information Processing, Vol. 28
Publication date31/12/1999
URLhttp://hdl.handle.net/1893/618
PublisherSpringer Verlag
Publisher URLhttp://www.springer.com/…?detailsPage=toc
Place of publicationAmsterdam
ISBN9780792386469
ConferenceFORTE XII /PSTV XIX '99 IFIP TC6/WG 6.1 Joint International Conference on Formal Description Techniques for Distributed Systems and Communication Protocols and Protocol Specification, Testing and Verification
Conference locationBeijing, China
Dates

People (1)

Professor KEN Turner

Professor KEN Turner

Emeritus Professor, Computing Science