Modelling Digital Logic in SDL

Citation

Csopaki G & Turner KJ (1997) Modelling Digital Logic in SDL. In: Mizuno T, Shiratori N, Higashino T & Togashi A (eds.) Formal Description Techniques and Protocol Specification, Testing and Verification. FORTE X / PSTV XVII '97. IFIP International Federation for Information Processing. FORTE/PSTV'97 - 1997 IFIP TC6/WG6.1 Joint International Conference on Formal Description Techniques (X) for Distributed Systems and Communication Protocols, and PROTOCOL SPECIFICATION, TESTING, AND VERIFICATION (XVII), Osaka, Japan, 18.11.1997-21.11.1997. Amsterdam: Springer Verlag, pp. 367-382. http://www.springer.com/computer/communications/book/978-0-412-82060-1?detailsPage=toc

Abstract
The specification of digital logic in SDL (Specification and Description Language) is investigated. A specification approach is proposed for multi-level descriptions of hardware behaviour and structure. The modelling method exploits features introduced in SDL-92. The approach also deals with the specification, analysis and simulation of timing aspects at any level in the specification of digital logic.