Concurrent Specification and Timing Analysis of Digital Hardware using SDL (extended version)

Citation

Turner KJ, Argul-Marin FJ & Laing SD (2000) Concurrent Specification and Timing Analysis of Digital Hardware using SDL (extended version). In: Rolim J (ed.) Parallel and Distributed Processing. Lecture Notes in Computer Science, Volume 1800. IPDPS 2000 - International Parallel & Distributed Processing Symposium, Cancun, Mexico, 01.05.2000-05.05.2000. Berlin: Springer Verlag, pp. 1001-1008. https://doi.org/10.1007/3-540-45591-4

Abstract
Digital hardware is treated as a collection of interacting parallel components. This permits the use of a standard formal technique for specification and analysis of circuit designs. The ANISEED method (Analysis In SDL Enhancing Electronic Design) is presented for specifying and analysing timing characteristics of hardware designs using SDL (Specification and Description Language). A signal carries a binary value and an optional time-stamp. Components and circuit designs are instances of block types in library packages. The library contains specifications of typical components in single/multi-bit and untimed/timed forms. Timing may be specified at an abstract, behavioural or structural level. Timing properties are investigated using an SDL simulator or validator. Consistency of temporal and functional aspects may be assessed between designs at different levels of detail. Timing characteristics of a design may also be inferred from validator traces. A variety of examples is used, ranging from a simple gate specification to realistic examples drawn from a standard hardware verification benchmark.

• conc-hw.pdf